There is already known a device called "Parallel Selfsynchronizing Scrambler" (indicated at 3 in FIG. 1) at the inputs thereof there are coupled four lines thereon there is respectively transmitted tributary data T1,T2,T3,T4 (at a frequency of 141 Mbits/sec ) and the four outputs thereof are coupled to a multiplexer 1 which is driven at 565 MHz by an oscillator or clock 2 (therewith a frequency divider is associated, indicated at 2a and provided for driving at 141 MHz the device 3); thus at the output A of the multiplexer 1 the data T1,T2,T3,T4 are effectively scrambled and are transmitted on the transmission line at a frequency of 565 M bits/sec.
The above mentioned devices 3 are however affected by known drawbacks, which can be resumed as follows:
(1) the line errors are three times greater
(2) there is necessary to provide additional logic control networks for reducing the possibility of having long recursive consecutive zero sequences.
In order to overcome the above mentioned drawbacks of the item (1) and (2) there is used the well known Reset Scrambler (which for example is recommended by the German and French Administrations) indicated in block form in FIG. 2.
In FIG. 2a the real scrambler, schematically indicated at 4, is actually a pseudo-random sequence source; said source or generator consists of seven like sequential blocks (or flip-flops) A1,A2,A3,A4,A5,A6,A7 at each thereof there have been indicated at D,Q,CK,PR respectively the input, output, clock input (as derived from the divider 2a supplying a clock pulse sequence having a frequency of about 141 MHz) and the preset input.
The outputs Q1,Q2,Q3,Q4,Q5,Q6 are directly coupled to the D inputs of the blocks A2,A3,A4,A5,A6,A7 respectively, while the outputs Q6,Q7 of the blocks A6,A7 are coupled to an Exclusive-OR 5, the output thereof is coupled to the D input of the block A1.
The tributary data T1,T2,T3,T4 are sent to corresponding AND logic circuits 6,7,8,9, jointly to the synchronization signal S (see FIG. 2a).
The outputs of the mentioned AND circuits are coupled to corresponding Exclusive-OR logic circuits 16,17,18,19 thereto there are respectively coupled the outputs Q2,Q1,Q7,Q5 of the blocks A2,A1,A7,A5. The outputs c,d,e,f of the circuits 16,17,18,19 are coupled to corresponding inputs of the multiplexer 1.
More specifically said multiplexer 1 provides at the output A thereof the data which are present at the inputs thereof, under the control of a logic block 10 and according to the truth table H1 of FIG. 2b; it should be noted that the input "a" of the logic block 10 is coupled to the output Q of the first of the two flip-flops 11a forming the frequency divider 2a, the remaining input b of that same logic block 10 being coupled to the output of an AND circuit 12 to the two inputs thereof there are respectively sent the synchronization signal S and the signal derived from the Q output of the second flip-flop 11b of the divider 2a.
The operation of the above illustrated circuitry of FIG. 2a may be easily desumed from the truth table of FIG. 2b.
More specifically the first column of said table indicates the elementary times 7 scanned by the clock signals supplied by the divider 2a, the columns from the second to the eighth indicate the logic levels of the mentioned outputs Q1,Q2,Q3,Q4,Q5,Q6,Q7, the ninth column indicates the logic levels of the present signal PR, the tenth column indicates the logic levels of the synchronization signal S, the columns from the eleventh to the fourteenth illustrate the signals G1,G2,G3,G4 of the source 4 used for the scrambling operation, and, finally columns from fifteenth to eighteenth indicate the logic levels of the signals sequentially sent in that order (that is from the fifteenth to the eighteenth column) at the output A of the multiplexer 1.
At the elementary time zero (first column) the present signal is .0. and the signal S is also .0.: the outputs of the blocks A1 . . . A7 are at a 1 logic level; in other words at the input A there are present the logic levels of the inputs c,d as it may be desumed from table H1.
At the second and third clock pulses (with the preset signal at the logic level 1), the signal S is again .0., thereby to the input A there are sequentially sent the logic levels present at the inputs c,d: thus, by three clock pulses, at the output A there is formed the frame aligning word F (FIG. 2b, table H2) which, as it is known, is: "1 1 1 1 1 .0. 1 .0. .0. .0. .0. .0. ".
At the fourth clock pulse, the signal S is "1", thereby all the four outputs Q2,Q1,Q7,Q5 of the blocks A2,A1,A7,A5 are used for carrying out the scrambling of the tributary signals T1,T2,T3,T4 (to this end see the contents of the fourth and following rows from the fifteenth to the eighteenth columns of table H2).
The device illustrated in FIG. 2a, in addition to overcoming the mentioned drawbacks of items (1) and (2) affords the great advantage that as it is reset it generates the mentioned hard copy frame aligning word F.
On the other hand, said Reset Scrambler is affected by a great drawback. In fact in the case therein the signals T1,T2,T3,T4 are of the periodic type, in particular T1=T2=T3=T4=.0., the multiplexed signal (at the output A) does not represent a pseudo-random succession of period 2.sup.7 --1, but a sequence with a rather approximative randomness, which is greatly objectionable, since in those cases it would be necessary to have sequences as random as possible.